- CS, DC, RST, and backlight pins must match the panel wiring. A swapped DC line looks like random pixels.
- Clock polarity/phase and max SPI rate differ by controller. Start slow, then raise the clock.
- Share the bus carefully with flash or SD. Wrong CS timing corrupts both the panel and storage.
- Init sequence and color order (RGB/BGR) are panel-specific. Copying another module’s init is a common miss.
Short answer
SPI TFT shows garbage or a white screen on ESP32. What usually breaks?
中文
短答
ESP32 上 SPI 屏花屏或白屏,常见卡点?
- CS、DC、RST、背光脚要和屏线一致。DC 接反会像随机噪点。
- 极性和最高时钟因控制器而异。先降速点亮,再提高时钟。
- 和 Flash/SD 共总线时 CS 时序要干净。CS 乱了屏和存储一起坏。
- 初始化与 RGB/BGR 顺序跟面板绑定。抄别的模组 init 很常见。